资源列表
TRANSMITTER
- 此程序为基于OFDM的802.11a的发送端的VERILOG程序，包含所有模块。-This program is VERILOG program sender 802.11a OFDM-based, including all modules.
Perfect-Timing-II-Book
- 该文档为英文的完美时序一书，写的很好，对FPGA时序设计很有帮助。-This document is the perfect timing of the English book, well written, useful for FPGA design timing.
A-(2)
- A SIMPLE MODEL A SIMPLE MODEL A SIMPLE MODEL A SIMPLE MODEL-A SIMPLE MODEL A SIMPLE MODEL A SIMPLE MODEL A SIMPLE MODEL A SIMPLE MODEL A SIMPLE MODEL
hdb3
- hdb3编解码程序，非常简洁好用，欢迎下载-hdb3 codec program is very simple to use, welcome to download
Desktop
- 此程序为矩阵键盘驱动Verilog程序，带键盘模型和仿真平台。-This is a matrix keyboard driver, Verilog, with simulation models and simulation platform
SERIALADDER
- SERIAL ADDER 8-BIT-SERIAL ADDER 8-BIT
SCCB_Control
- 两线式SCCB总线FPGA驱动，verilog语言编写，可用于配置OV系列摄像头-Two-wire bus SCCB FPGA drive, verilog language, can be used to configure the OV series camera
mux_structural
- 8 to 1 16bit mux code for ECE585 of IIT
epm3128a
- dsp28335，索思达电子开发板28335evm-1开发板搭载的CPLDepm3128a的VHDL核心源代码-dsp28335, Suo Sida electronic board 28335evm-1 development board equipped CPLDepm3128a of VHDL core source code
freq_div
- //奇数倍分频器基于verilog HDL.-(ODD number)Freq Divider based on Verilog HDL.
SDRAM_Verilog
- 本源码由Verilog语言编写，用硬件实现SDRAM的读写和存储数据功能，包括SDRAM的控制模块、初始化模块、读写模块等！-The source the Verilog language, implemented in hardware SDRAM read and write and store data, including SDRAM control module, initialization module, reader module, etc!
AD0804LC
- 使用VHDL语言完成了ADC0804程序,设定阈值，过阈值报警。附带了整个工程文件-with VHDL language,it can work with ADC0804