资源列表
LCD_1602
- 基于C8051单片机中应用LCD1602的详细代码，已经封装成库，及一个.C一个.H文件-C8051 MCU based applications LCD1602 detailed code has been packaged into a library, and one. C a. H files
uart
- uart source code using vhdl
VHDLSecondAndOther
- VHDL 秒表 计数器 等等的实验课程的优秀程序集，适合初学者学习-VHDL second and other
i2c
- 按动开发板键盘某个键CPLD将拨码开关的数据写入EEPROM的某个地址，按动另外一个键，将刚写入的数据 -- 读回CPLD，并在数码管上显-Pressing a button keyboard CPLD development board DIP switches, the data will be written to EEPROM in an address, pressing another key, the newly written data- read back CPLD, an
4wei-ji-shu-qi
- 4位同步二进制加法计数器的工作原理是指当时钟信号clk的上升沿到来时，且复位信号clr低电平有效时，就把计数器的状态清0。 在clr复位信号无效（即此时高电平有效）的前提下，当clk的上升沿到来时，如果计数器原态是15，计数器回到0态，否则计数器的状态将加1. -4 synchronous binary adder counter works by the rising edge of the clock signal clk, and the reset signal CLR acti
add-based-on-vhdl
- 1位和4位加法器的VHDL硬件描述语言实现，可用quaturs实现。-add based on VHDL
DAC0832-VHDL-design
- DAC0832接口的VHDL设计实现。利用硬件描述语言在FPGA上实现DAC功能。-DAC0832 interface VHDL design and implementation. Using hardware descr iption language DAC function in the FPGA.
adc_verilog
- adc verilog 用verilog编写的sigma-delta adc例子 应用在计量类adc产品
FineMeasure
- a ranging fine measure function
aes_decrypt
- This the Top Module for AES Decryption algorithm-This is the Top Module for AES Decryption algorithm
M2SDRAM_MR
- gray code based FIFO
8.6DAC0832
- FPGA中用VHDL编写的DA8032的接口电路及程序源码-DA8032 prepared using VHDL FPGA interface circuit and program source code