资源列表
adder
- 详细介绍多种方法实现加法器，有行为级，结构级，数据流级等，适合初学者迅速掌握Verilog语言。-Different methods of achieving adder is divided into behavioral, structural level, the data flow level, etc., suitable for beginners to quickly master the Verilog programming language
FIR-filter
- this program for demonstration how work is a FIR filter
JTAG-control
- this program for demonstration how work is finite control the jtag
microprogramming
- this program for demonstration how work is a FIR filter with microprogramming control
binbcd8
- Binary to BCD conversion in VHDL for implementation in FPGA
ASCII_PACKAGE
- ASCI package in VHDL for verilog implementation
lfsr_top
- LP LFSR for low power test pattern generation_V
LP-LFSR
- LPLFSR for Low power test pattern generation_V
SPI_veeren
- Serial peripheral interface using verilog
viterbi_decode_veeren
- Viterbi decoding algorithm
Viterbi_algorithm_VeeRen
- Viterbi algorithm using Verilog
SPI_verilog_veeRen
- serial peripheral interface using tx and rx