资源列表
FIFO-queue-using-a-DPRAM
- FIFO queiue using DPRAM goog project
RISC-CODE
- Design and Implementation of 16 Bit RISC Processor
EGPWS
- INTEGRATION OF EMERGENCY LOCATOR TRANSMITTER (ELT) OF AIRCRAFT WITH THE GLOBAL POSITIONING SYSTEM (GPS)RECEIVER - A VLSI DESIGN APPROACH
nand_controller
- this the nand flash controller having testbench and simulation model for nand flash in it-this is the nand flash controller having testbench and simulation model for nand flash in it
ahb_master_latest.tar
- IN THIS WE HAVE AHP bus master for burst data transfer
ahb_slave_latest.tar
- In this we have APB bus slave for burst data transfer
a7
- THIS is the file consists of verification environment for SWITCH(DUT)
registerbank
- THIS file consists of register bank and its testbench
m_wallace_coding
- Wallace tree Multiplier
ug940-vivado-embedded
- Vivado Design Suite Tutorial 是学习Vivado 入门文档，源自xilinx，权威易懂 -Vivado Design Suite Tutorial Learning Vivado entry documents, xilinx, authoritative and easy to understand
xapp1082-zynq-eth
- PS and PL Ethernet Performance and Jumbo Frame Support with PL Ethernet in the Zynq-7000 AP SoC 是学习Vivado 入门文档，源自xilinx，权威易懂 -PS and PL Ethernet Performance and Jumbo Frame Support with PL Ethernet in the Zynq-7000 AP SoC Learning Vivado entr
Avnet_V5FXT
- Avnet_V5FXT_Development_Board_Embedded_Design 是学习FPGA嵌入式入门文档，源自xilinx，权威易懂 -Avnet_V5FXT_Development_Board_Embedded_DesignFPGA embedded learning introductory document xilinx, authoritative and easy to understand