资源列表
2_03_addder8
- 学习xilinx的简单模块程序，熟悉xilinx开发平台ise-xilinx demo code
7_06_FifoSim
- 学习使用xilinx的简单例程，熟悉ise平台-xilinx demo code
7_07_DCMSim
- 学习使用xilinx的简单例程，熟悉ise平台。DCM 仿真。-xilinx demo code
DIVIDER
- M进制计数器 verilog code for divider-verilog code for divider verilog code for dividerverilog code for divider
nrf
- 基于fpga的无线传输nrfl24l01代码，这是发送和接收的代码，注意改下芯片的型号和引脚-nrf24l01 and fpga
shuzizhonganjian
- 设计一个数字钟，本设计要求一个12进制或24进制的具有时、分、秒计时功能的数字钟，并能进行时和分的调整。-Design a digital clock, this design requires a 12 or 24 hexadecimal hexadecimal have the hours, minutes, seconds, chronograph function digital clock, and can be adjusted hours and minutes.
ma_slice_temp
- verilog code temp h-verilog code temp hahahah
lab4
- 用VHDL以实现键盘输入的电路，包括测试文件-to realize keyboard funtion
meimei
- 电子时钟，可以显示时间，年月日，运动秒表，闹铃-Electronic clock that can display time, date, sports stopwatch, alarm
final-project
- final project- design processor
Architecture-for-Dataflow-Graphs-with-Feedback.ra
- Architecture for Dataflow Graphs with Feedback
VHDL_-position-control
- 本程序用VHDL语言编写的步进电机定位控制程序-This program written in VHDL language of stepper motor positioning control program