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  1. VHDL_ALTERA_MAX-EPM570-RS232_USB-TTL

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  2. ALTERA MAX-II-EPM570 VHDL example RS232_USB-TTL schematic 21EDA.-ALTERA MAX-II-EPM570 VHDL example RS232_USB-TTL schematic 21EDA.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-01
    • 文件大小:467.72kb
    • 提供者:Raminiut
  1. VHDL-Lab1

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  2. It is a good programming tech to design fpgas and ICs.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-03
    • 文件大小:607.28kb
    • 提供者:Madan Neupane
  1. VHDL-lab4

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  2. VHDL stands for Very High speed IC Hardware descr iption language.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-29
    • 文件大小:348.49kb
    • 提供者:Madan Neupane
  1. bpsk

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  2. BPSK- Design and implementation of BSPK modulation and demodulation.. using sine wave-BPSK- Design and implementation of BSPK modulation and demodulation.. using sine wave..
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-29
    • 文件大小:296.99kb
    • 提供者:kalyan
  1. dmf_vhdl

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  2. digital Matched Filter design - including the clock synchronization of the design and its implementation-digital Matched Filter design - including the clock synchronization of the design and its implementation..
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-27
    • 文件大小:412.76kb
    • 提供者:kalyan
  1. dptaal

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  2. Design of Adiabatic logic using VHDL
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-24
    • 文件大小:346.54kb
    • 提供者:kalyan
  1. COMB

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  2. We use port map statement to achieve the structural model (components instantiations). The following example shows how to write the program to incorporate multiple components in the design of a more complex circuit. In order to simulate the design, a
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-31
    • 文件大小:820byte
    • 提供者:sam
  1. CALIBRATION

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  2. Calibration is a comparison between measurements – one of known magnitude or correctness made or set with one device and another measurement made in as similar a way as possible with a second device. The device with the known or assigned correctness
  3. 所属分类:VHDL-FPGA-Verilog

  1. all-code-files

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  2. code for virus detection processor in vhdl
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-29
    • 文件大小:16.52kb
    • 提供者:kusumanchi
  1. finalcode

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  2. vhdl code for simple virus detection processor. it can also develop in verilog
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-29
    • 文件大小:13.74kb
    • 提供者:kusumanchi
  1. d-Flip-Flop

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  2. D flip flop and some other codes added together recomended use is adding layer not use in a single bench
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-13
    • 文件大小:1.54kb
    • 提供者:Dou
  1. mux8to1_with_if

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  2. this code to input 8 different data and make them out sequentialy -this code to input 8 different data and make them out sequentialy
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-16
    • 文件大小:17.8kb
    • 提供者:freaker
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