资源列表
axi_dispctrl
- zynq AXI display controller source for zybo
DE2_115_PS2_DEMO
- 完成确定鼠标目前的位置X,Y轴，以及对鼠标三键的检测。-Completion determination mouse current position X, Y-axis, and detection of mouse triple bond.
UG586-7SeriesDMIUserGuide
- UG586 - Zynq-7000 All Programmable SoC and 7 Series Devices Memory Interface Solutions v2.3 User Guide ( ver2.3, 18511 KB )-UG586- Zynq-7000 All Programmable SoC and 7 Series Devices Memory Interface Solutions v2.3 User Guide ( ver2.3, 18511 KB )
manchester_encoder
- 曼切斯特码解码器verilog程序，已通过ModelSIM仿真，可用-Chester Verilog decoder procedures, has been through the ModelSIM simulation, the available
x16_to_boc32
- 16位串行数据转32位并行数据Verilog程序，已通过仿真，可用-The 16 bit serial data to 32 bit parallel data Verilog procedures, has been through the simulation, the available
a_vhd_16550_uart_latest.tar
- 串口程序，基于16550内核，有不同的版本，比较齐全。-the UART program，based on 16550 core，have several versions。
spartan5
- vhdl program for adc of spsrtan 3e
netlist
- vhdl program of matlab file converted to vhdl
netlist8
- vhdl program of matlab file converted to vhdl
netlist2
- vhdl program of matlab file converted to vhdl
exa1
- 8位全加器，为EDA的第一个实验，由半加器和或门组成-8 full adder bit EDA experiment first simple experiment, through the OR gate constructed with half-adder
exa1_adder
- 之前上传的是全加器，这个是自己设计的8位全加器，8位并行全加器-Before uploading the full adder, this is their own design eight full adders, eight parallel full adder