资源列表
SynchronizeAutomaticallyEntersCPLD
- CPLD与CY7C68013通讯程序，使用的是同步输入功能，测试过了可以使用，需要下载自动同步驶入的固件。-CPLD and CY7C68013 communication program that uses synchronous input function test can be used, you need to download the firmware automatically synchronized into.
FPGAPRJ
- NIOS 基于 cyclone 2 的工程 -NIOS based engineering cyclone 2
TX
- 串口发送控制程序！在一帧的发送下，经过串口协议编写的硬件描述语言verilog！-Serial transmission control program!
RX
- 串口接收程序源码，经过实际验证的最终版本，接收的操作！-Serial port to receive program source code, the actual verification of the final version after receiving operation!
SOS
- 基于verilog的sos求救信号的编写，适用于quartus ii的开发环境！-Verilog based distress signal written in sos, apply quartus ii development environment!
SignalTap_Test
- 基于quartus ii的SignalTap的测试文件编写，富有测试后的时序文件！-Based on the SignalTap quartus ii test documentation, full test series after the file!
PWM
- 在verilog开发环境下针对pwm信号的占空比的调节的编写调试！-In the development environment for verilog pwm signal duty cycle regulated write debugging!
spi_dac_max5309
- dac 与FPGA的SPI接口通信 , SPI 接口协议请查阅网络相关资料-communication between FPGA and DAC max5309
sdram_mdgray1test
- 使用特权EP1C的开发板，实现数码相框加灰度化功能，用verilog编程。-Privileged EP1C development board to achieve digital photo frame features plus gray, with verilog programming.
EDA
- EDA小程序，用VHDL语言设计七人表决器，四位加法器。-EDA small program design using VHDL seven people voting, four adder.
EDA-miaobiao
- EDA课程设计，作为秒计数器的系统时钟512Hz，秒表计数为两位BCD计数，具有减计数和加计数功能-EDA curriculum design, as the seconds counter system clock 512Hz, stopwatch count as two BCD counting, counting and processing has reduced counting function
VerifMeSystemVerilog
- System verilog的一本英文资料书，介绍了system verilog的语法，使用方法，以及如何验证-System verilog of a book information in English, introduced the system verilog syntax, usage, and how to verify