资源列表
dsp_link_tx16
- FPGA到TS201的link_port接口，以16位的数据格式传输到DSP。-FPGA to TS201 s link_port interface, 16-bit data format for transmission to the DSP.
DSCH2
- VLSI compiler or nano chip designer.
lec_Chap2
- Verilog Hardware Descr iptive Language
source
- VHDL Altera example code
phase-locked-loop-implementation
- 在FM0数据解码时，利用锁相环生成数据同步时钟信号。文件为锁相环实现。Verilog HDL-When FM0 decoding data using the phase-locked loop generates the data synchronizing clock signal. File for phase-locked loop implementation.Verilog HDL
decode
- 通信数据中FM0数据的解码接收，解码数据和输出同步时钟。Verilog HDL-FM0 decoding the received data in the communication data, the decoded data and outputs sync clock。Verilog HDL
normCORDIC_VHDL
- 用VHDL写的CORDIC算法下求距离的一个模块，经测试可用精度高-By seeking lower write VHDL distance CORDIC algorithm module, the test can be used with high precision
eup
- It is the HDL and MATLAB code for image processing in Modelsim.
TVout
- TV Output for Xilinx FPGAs
WS2812B_deneme
- WS2812B strip driver sample
EPM3032
- EPM3032上使用quartus5.0编写的verilog程序，用于单片机译码并驱动外设之用。-A verilog program used for embeded cpu encode and drive pheripha chip,platform is quartus5.0
simple-counter
- Simple counter in verilog