资源列表
des
- this is des code of vhdl version.
adc
- 设计ADC控制器，Verilog代码.利用有限状态机设计方法在FPGA上设计ADC0809的接口控制器，采样结果送到数码管显示出来。-ADC controller design, Verilog code using finite state machine design in the FPGA design ADC0809 interface controller, the sampling results to the digital display.
i2c
- 基于FPGA 的I2C总线，读写数码管显示-FPGA based on the I2C bus read and write, digital tube display
Asynchronous-FIFO-Design
- 异步FIFO设计，一共包含6个模块，使用的硬件描述语言verilog。-Asynchronous FIFO design,including six modules.HDL language is verilog.
iBoard_TFT_Driver_SRC_V1.00
- iboard 4.3寸 480*272 tft CPLD驱动代码 基于verilog 可直接使用STM32 FSMC控制-iboard 4.3 inch 480* 272 tft CPLD driver code based on verilog. it can directly use STM32 FSMC bus control this driver
mult
- 自己编写的乘法器 二进制4*4 vhdl环境 仿真通过-On time-multiplier binary imagecut.rar 4* 4 VHDL environmental simulation through
sycclk
- it s modul of clock in fpga vhdl where the cycle is 25 MHz enjoy
chengxu
- 设计状态机从SRAM中读取数据，并相加，即求SRAM【7：0】【2：0】中8个字节数的和并输出，SRAM为内置RAM-Design state machine to read data from the SRAM, and added, that is seeking SRAM [7:0] [2:0] 8 bytes and output, SRAM built-in RAM
tony_wu
- Verilog HDL程序 Verilog HDL程序-Verilog HDL procedural procedures Verilog HDL
crc
- 用于ethernet的CRC校验源代码，ALTERA官方代码，已验证-CRC checksum of the source code for ethernet, ALTERA official code, verified
shuzilvboqideyingjianshixian
- 数字滤波器的硬件实现，里面实例可以直接在quartus中运行-Digital Filter hardware, which can be directly examples run in quartus
blauxe_4v8b_2d1e
- 4路数据光端机，光纤传输485或232数据控制球机云台，经过验证无问题-four data link