资源列表
generadorfrecuencia
- Frecuenzy generator with the following in and out, Frecuencia : IN STD_LOGIC_VECTOR(3 DOWNTO 0) CLK : IN STD_LOGIC CLKOut : OUT STD_LOGIC-Frecuenzy generator with the following in and out, Frecuencia : IN STD_LOGIC_VECTOR(3 DOWNTO 0
pll_100M
- pll debug code,for quartus fpga,vhdl code for straxtix.
freqm.verfinal
- 基于xlinx FPGA的频率计，顶层文件为freqm.v 可以直接仿真或烧写。通过外部选择闸门时间可实现不同量程。闸门时间有1s，0.1s，0.01s，0.001s可选。数码管显示6位数值。最高可测99M的信号输入。-Based on xlinx FPGA frequency meter, top-level file for freqm.v direct simulation or programming. External to select the gate time can be a
digital-frequency-meter
- VHDL实现的 数字频率计 数字频率合成DDS-VHDL implementation of the digital frequency meter DDS
lcd
- 组合逻辑电路设计：实现9种逻辑运算、6种移位运算以及高低双字节内容互换。 -Combinational logic circuit design: Implementation of 9 logical operations, six kinds of double-byte shift operation, as well as the level of content exchange.
83
- 基于FPGA的83优先编码器源代码，赛林思比赛专用-Based on FPGA 83 priority encoder the source code, and the "special LinSi game
txt_util
- VHDL库，仿真时使用的，包括打印，类型转换等实用的操作-Practical operation VHDL library, using simulation, including print, type conversion, etc.
通用异步收发器
- 用Verilog编写的uart通用异步收发器带testbench
Fix-data-send-UART
- Fix data UART send and receive verilog codes.
fpj
- 课程设计-分频计 能够很好的实现分频功能
vhdl_learn
- vhdl learning basic level
jtag
- Fpga开发应用，jtag方面的源代码，VHDL-Fpga development and application, jtag in the source code, VHDL