资源列表
class12_uart_rx
- verilog编写的串口接收程序，学习串口的话可以用作参考，已经实际验证过-Verilog prepared by the serial receiving procedures, learning serial port can be used as a reference, has been verified
Verilog.rar
- 比较经典的verilog学习书籍，内有丰富的程序实例。,Verilog study compared the classic books, there are abundant examples of the procedures.
Design_Compiler
- Design Comliler 教程-Design Comliler Tutorial
DesignCompiler
- Design Compiler使用简要说明,说明了用这一工具进行综合的过程 -use Design Compiler brief statement, the use of this tool for integrated process
zhengxuanbo
- 实现了正弦波的功能，利用ram和计数器，采用原理图编辑的-Achieved a sine wave functions, the use of ram and counters, using the schematic editor
S2C-Dual-Virtex-6
- S2C Dual Virtex-6 TAI LM datasheet
VerilogHDL
- 完整的九层电梯控制器verilog源代码-Complete nine-story elevator controller Verilog source code
VHDL3p2a
- VHDL Quick Learning Material
shizi39
- 闹钟设计，基于fpga的多功能闹钟设计，时钟设计-Alarm clock design, design fpga-based multi-function alarm clock, clock design
sd-2.0-Specification
- Sd Card System 2.0 Specifiction.真实完整版。独此一家。-Sd Card System 2.0 Specifiction. A true and complete version. Alone this one.
DS1307_LCD.通过IIC总线读写实时时钟DS1307
- 通过IIC总线读写实时时钟DS1307，并把时、分、秒显示在12864液晶屏上，用的CycloneII EP2C8，Quartus环境,Through the IIC bus read and write real-time clock, DS1307, and the hours, minutes and seconds displayed on the LCD screen on the 12864, used CycloneII EP2C8, Quartus environment
uart2spi_latest.tar
- UART转SPI IP核，测试可用，包括测试文件，Modelsim环境-UART to SPI IP core test available, including test papers, Modelsim environment