资源列表
Protel-dxp-operating-skills-summary
- 详细介绍Protel DXP 操作技巧，包括封装库的设计，原理图的设计-Details Protel DXP operating skills, including package library design, schematic design, etc.
mp3_designtest
- MP3 player source code
HardCopy
- HardCopy的器件介绍，用于初学者了解ALTERA的器件参数-A descr iption of the Ethernet Tester
led
- 此书是针对于初学者而写的一本教程,里面对 LED 的各方 面进行了详细的介绍,,让初学者能够在很短的时候了解 LED 相关各种参数指标，LED 驱动，LED 应用的注意事 项等等，此书已经帮助了很多初学者和销售员，对初学者 和销售员来说,是一本入门极好的秘籍。 -This book is written for beginners but a tutorial, which the various aspects of the LED described in detail, s
time
- 利用quatars,vhdl实现有倒计时功能计时器，设计定时器功能有正向计时和倒向计时，可暂停计数，继续计数。当倒向计时计数为0时会报警（时间为1分钟）在报警期间可以认为关闭-Using quataus, VHDL realization which has the function of the countdown counter, timer design features are timing and backward timing, can suspend count, continue
DataAcquisitionCard
- usb2.0的高速数据采集卡ISE工程包，包括了完整的设计-usb2.0 high-speed data acquisition card ISE project package, including a complete design
hdl-master
- AD9361的ip核，已经调试通过，在vivado上可以运行通。AD9361是一个双通道的便捷收发器，通常用于3G/4G基站。-AD9361' s ip nuclear, debugging has been passed on vivado can run through. AD9361 is a dual-channel transceiver convenient, usually used in 3G/4G base stations.
DELAY1
- 本程序以ISE为开发平台，采用VHDL为开发语言，实现了对一个时钟信号延时的功能-the procedures to ISE for the development platform for the development of VHDL language, Implementation of a clock signal delay function
PN_m.sequence
- 关于编译的一个3位伪随机序列源文件，简单实用，适合作例题看！-Compiled on a three pseudo-random sequence of source files, simple and practical, suitable for example to see!
Verilog
- VERILOG语言的学习，更好的运用CPLD，FPGA-VERILOG language learning, better use of CPLD, FPGA
veriloghdl
- 学习VERILOG的一些资料，包含理论和一些实例，很有用的-VERILOG learn some of the information, including the theory and some examples, very useful
Debussy-learning
- Debussy仿真软件使用方法及配套的实例代码。很详细的介绍了Debussy软件的使用方法，结合Modelsim来使用-Debussy simulation software use and supporting examples of code. Very detailed descr iption of the use of Debussy software, combined with Modelsim to use