资源列表
catapult_lb_useref
- 非常好的catapult学习书, catabult 可用于高级综合，由c产生vhdl/verilog。这本关于自建高级综合单元。-very nice book for catabult study， this is for liburay building
Verilog-classic-tutorial
- Verilog经典教程，非常好的资料！值得一看！-Classic Verilog tutorials, very good information! Worth a visit!
Verilog_Guideline
- Verilog经典教程，有非常详细的解答以及实例-Verilog classic tutorial, very detailed answers and examples
fifosy
- 用于对Xilinx FPGA FIFO的控制及读写-Xilinx FPGA FIFO
USB
- 使用标准VHDL编写的USB协议，可在CPLD或FPGA上实现USB功能。-use VHDL to implement USB protocol, which can be used in CPLD or FPGA
stop_watch_1kHz
- stop_watch vhdl code
output_10014537
- XINLIX SPORTAN3 FPGA 可在数码管上显示滚动的数字，可自由设置，程序设计时钟分频等-XINLIX SPORTAN3 FPGA in the digital tube display scroll figures can be set free, program design clock divider, etc.
vhdl
- 10秒计数器模块ＶＨＤＬ源程序，在FPGA中实现计数器功能(10 seconds counter module VHDL source code, in FPGA realize counter function)
paobiao
- 数字跑表，实现分秒模块，一份独创的代码程序，请大家下载，-this is a good thing
lab8_wena_Arturo
- vga verilog code for showing the vga pattern and diferent functions for a Spartan develp card
MapAlgorithm
- However, turbo equalizers can be computationally complex and hence require significant power consumption. In this paper, we present an energy-efficient VLSI architecture for such linear turbo equalizers. Key architectural techniques include elimi
led_horse
- 跑马灯led_horse vhdl cpld\fpga-led_horse vhdl cpld\fpga