资源列表
fft
- FFT快速傅里变换的C++实现,已经通过调试，可以借鉴-the realization of fft algorithem
FIFO
- fifi asyncronous and syncronus
miaobiao
- 秒表计时功能,可以从零记到九十九，可以暂停，可以清零。-Stopwatch functions, from zero in mind to 99, you can pause, can be cleared.
SW_LCD1602_irq
- SW_LCD1602_irq是nios中实现按键中断以及lcd1602显示-SW_LCD1602_irq is implemented nios interrupt button and display lcd1602
V35interface-communicate
- V.35接口与E1接口之间转换的基本原理,介绍了E1信道分时隙通信的基本过程，叙述了基于FPGA用VHDL和QuartusII来仿真本系统设计与实现的过程。-V.35 interface and E1 interface to convert between the basic principles of E1 channel introduces the basic process of communication sub-time slot, described by VHDL and FP
MSP430149heFPGAtongxindds
- MSP430149与FPGA通信附带dds程序，这个程序是通过硬件实现功能了的，大家可以放心的下载-MSP430149 communication with the FPGA with dds program that functions through a hardware implementation, and we can be assured of the download
verilog-pll
- 用verilog写的倍频电路 文件中介绍DP-The multiplier circuit file by verilog introduced DPLL
sp605_IBERT_rdf0036_13.3_c
- 此文件是用所需的时钟缓冲器岁设计示例顶部包装。用户逻辑可以在此包装和岁设计实例化。XILINX官方参考设计。-This file is an example top wrapper for the ibert design with the required clock buffers. User logic can be instantiated in this wrapper along with the ibert design.
Small-multiplier
- 小型倍频器，简单的介绍了如何用verilog写倍频电路》-Small multiplier
BASYS_DDS
- fpga 实现dds,共享给大家了，如果有问题请交流，-fpga implementation dds, for everyone to share, if there is a problem, please exchange, thank you
vlogref
- cadence verilog reference
bc7281
- bc7281能够最大限度的节约IO口控制键盘和数码管最多能控制64个按键-the bc7281 savings to maximize IO port control keyboard and digital control can control up to 64 keys