资源列表
UARTReceiver
- serial communication using uart FPGA-based embedded system
Freq_Divider
- frequency divider fpga get slow frequency
DE2_PWM
- RC servo controller system using DE2
asymmetric_fifo
- 高速同步非对称FIFO,verilog 代码，很有价值的参考设计。-Asymmetric high-speed synchronous FIFO, verilog code, and very valuable reference design.
statemachinecontroller
- it is a vhdl code for a state machine controller
150M
- quartus_nios 综合开发平台，可以多中断，重要的是它的cpu可以工作在150M，总线工作在100M×32bit；-quartus_nios comprehensive development platform that can interrupt more important is that it' s cpu can operate at 150M, bus work in 100M × 32bit
0_F
- 译码（把二进制转化成十进制，七段码）vhdl语言，适用于初学者-yima
hexc_display
- 数码管显示的VHDL程序，自己做实验调出来的-LED display of the VHDL program, tune out their own experiments
vote7
- 自己设计的一个其人投票系统，对于VHDL初学者可以参考下-One of their own design their human voting system, for VHDL beginners can refer to the following
waveform
- 自己做的一个波形发生器，有兴趣的可以看下-Myself as a waveform generator may be interested in Kanxia
yiwei2
- 16位并行数据转换成串行数据，适用于FPGA与单片几之间的通信问题 （VHDL 编程）-FPGA VHDL
e004_veriloghdl
- Verilog编程语言，介绍了该编程语言的一些重要信息。非常适合初学者-Verilog programming language, introduced by the programming language, some important information. Very suitable for beginners