资源列表
Example25
- 设计一款基于VHDL的数码锁的小程序，其中加入了数码管显示功能及报警系统-VHDL-based design a digital lock small program, which joined the digital display and alarm system
Example19
- 设计一款基于VHDL的四人抢答器的小程序，按键按下开始抢答，首先按下的键值被数码管显示出来，与此同时，其它按键失去抢答作用。-VHDL-based design a small four Responder program, press the Start button to answer, first press the digital keys are displayed at the same time, other keys lost Responder role.
NIOSIIf_100M_Custom_NixieTube
- 挂载到Avalon-MM总线的数码管控制器-Avalon-MM bus to mount the digital controller
viterbia
- 实现viterbi译码，通过比较最小汉明距来判别最佳路径，删除不必要的路径，最终找到最佳路径。-Implement viterbi decoding, by comparing the minimum hamming distance to distinguish the best path, delete unnecessary path, finally find the best path.
DWT_Final_Delivery
- This is Discrete wavelet transform based IEEE object...this is developed in vhdl
High-Throughput-DA-Based-DCT-With-High-Accuracy.r
- This is Discrete wavelet transform based IEEE object...this is developed in vhdl
BusMultiplexer
- 基于DSP48E1的BUS MULTIPLEXER-Based on the BUS MULTIPLEXER DSP48E1
CLZ32
- 针对32位MIPS微处理器中CLZ指令（对单个字高位连零进行计数）的实现电路，使用了类似于超前进位的逻辑结构。包含测试文档，以及Design Compile所用的环境和脚本。-The CLZ instruction counts the number of leading zeros in a word. The 32-bit word in the GPR rs is scanned from most-significant to least-significant bit.The n
Vhdl1
- VHDL语言编写Verilog，实现数码管上数字循环显示-VHDL language Verilog, to realize the digital tube display digital loop
VHDL
- 关于学习FPGA很有用的资料，本人受益很大，愿与大家分享-About learning FPGA useful information, I benefited greatly, and is willing to share with you
FPGA-teach1
- 这是一种Verilog语言的学习资料的第一部分，能够很深入的帮助学习进步-This is the first part of a Verilog language learning materials, and can be very in-depth help learning progress
FPGA-TEACH2
- 同上一个类似，也是FPGA的学习帮助资料，很受益！-Ditto a similar, but also to help FPGA learning materials, very beneficial!