资源列表
rdf0125_fft_sim_tutorial
- FPGA硬件协仿真，采用jtag的仿真例子，如果自己设计的板卡，需要加上BSP文件，bsp的文件格式在fpga的安装目录-ISim Hardware Co-Simulation Tutorial: Accelerating Floating Point Fast Fourier Transform Simulation
EDK_IP_ISE
- 最近忙一个EDK的小工程，自己定义个用Create or Import Peripheral 定义了IP，在里面要用到ISE的IP.困扰了一段时间！经过群里、论坛上一些朋友的帮助 终于OK了-EDK little busy recently a project with their own definition of a Create or Import Peripheral define the IP, in which to use the ISE IP. Troubled for some
windows-script
- 在window平台，采用脚本TCL来编译fpga的经典例子。具体的写法，见工程中的ise_flow.bat文件。如果在工作站来处理更块-In the window platform, using classic example TCL scr ipt to compile the fpga. Specific wording, see the project ise_flow.bat file. If the workstation to handle more blocks
Zed_vga_hdmi_720p
- 开发板zedboard上的hdmi的显示，采用开发工具ise，熟悉ideo的时序，推荐给大家-Hdmi display board zedboard on using development tools ise, familiar ideo timing and recommend it to everyone
OLED_on_ZedBoard-master
- 开发板zedboard上的OLED的控制，采用开发工具ise，熟悉OLED的工作原理，推荐给大家-Control board zedboard on OLED development, the use of development tools ise, familiar OLED works, recommend it to everyone
Getting-Started-with-HW
- 采用zedboard、zynq等在matlab的平台上进行硬件协仿真的，文章介绍Getting Started with HW，环境的搭建和调试方式。-Using zedboard, zynq etc. on matlab platform for hardware co-simulation, the article describes the Getting Started with HW, build and debug mode environment.
mbq_ResetUSB
- USB controller reset
VHDL-8-wei-quan-jia-qi
- 原理图输入法实现8位全加器，内含vhd源码文件和一份word介绍文件，管脚配置已经完成，芯片为EPIK30TCI443-Schematic entry method 8-bit full adder, and a source code file containing the vhd file word descr iption, pin configuration has been completed, the chip is EPIK30TCI443
yi-wei-er-jin-zhi-quan-jia-qi
- 一位二进制全加器的源代码及详细WORD文档，maxplus软件运行，管脚已配置完成，芯片为EP1K30TC144-3-A binary full source code and detailed documentation WORD, maxplus software running, pin has been configured, EP1K30TC144-3
shu-kong-fen-pin-qi
- 数控分频器的源代码及详细WORD文档，maxplus软件运行，管脚已配置完成，芯片为EP1K30TC144-3-NC divider source code and detailed documentation WORD, maxplus software running, pin has been configured, the chip is EP1K30TC144-3
jia-fa-ji-shu-qi
- 含异步清零和同步使能的加法计数器的源代码，用maxplus软件运行，管脚已配置完成，芯片为EP1K30TC144-3-Asynchronous and synchronous cleared with the addition of the counter enable source code, run the software with maxplus Pin has been configured, the chip is EP1K30TC144-3
XU-LIE-JIAN-CE-QI
- 用状态机实现序列检测器的源代码，用maxplus软件运行，管脚已配置完成，芯片为EP1K30TC144-3-State of mind achieved with a sequence detector source code, run the software with maxplus Pin has been configured, the chip is EP1K30TC144-3