资源列表
fpga1
- 移动通信直放站数字滤波器的设计及FPGA实现 -Mobile communications repeater digital filter design and FPGA realization mobile communication repeater digital filter design and FPGA realization
fpga2
- 基于FPGA的有限冲激响应数字滤波器的研究及实现 -FPGA-based Finite Impulse Response digital filter of the research and realized FPGA-based Finite Impulse Response digital filter of the research and realized
1
- 毕业设计手册模版--数字滤波器的FPGA实现南才北往 毕业设计手册模版--数字滤波器的FPGA实现南才北往 -Graduation project handbook template- the FPGA realization of digital filters to the north to the south graduated from Design Manual template- the FPGA realization of digital filters to the nort
1
- 硬件编程设计,Quartus程序的源码,注释详细,是你学校FPGA/QuartusII的好代码!-Programming hardware, Quartus source process, comments in detail, is your school FPGA/QuartusII good code!
trafficlight
- 交通指示灯程序，VHDL语言，用于爱迪克实验箱模拟实验。-Traffic light program, VHDL language, for me love Dick simulation experiment.
RD1011_rev01.2
- 采用VHDL实现的UART硬件模块，该模块包括了modem的硬件实现，已经仿真测试代码，顶层模块可以采用VHDL或verilog实现，便于嵌入到自己的设计之中。文档中附有详细的使用说明和注释。-Achieved using VHDL hardware UART module, the module includes the hardware modem has simulation test code modules can be used top-level VHDL or verilog t
RealizationofdigitaldownconversionbyFPGA
- 介绍在FPGA 器件上如何实现单通道数字下变频（DDC）系统。利用编写VHDL 程序和调用部分IP 核相结合的方法研究了数字下变频的FPGA 实现方法,并且完成了其主要模块的仿真和调试,并进行初步系统级验证。-Introduced in the FPGA device on how to achieve the single-channel digital down conversion (DDC) system. VHDL procedures and the use of the prepa
caiyang
- 种用FPGA 实现对高速A/ D 转换芯片的控制电路,系统以MAX125 为例,详细介绍了含有FIFO 存储器的A/ D 采样控制电路的设计方法,并给出了A/D 采样控制电路的V HDL 源程序和整个采样存储的顶层电路原理图.-Species with FPGA to achieve high-speed A/D conversion chip control circuit, the system as an example to MAX125 details FIFO memory cont
FIFO_Buffer
- Verilog的FIFO源代码，可综合，并以运用到具体工程中-Verilog source code of the FIFO can be integrated and applied to specific projects
EXP4_sec
- 秒表 4个7数码管中的任何一个显示任意按键按下的次数。初始值为0，当计数到9时，下一次数值为0。利用Verilog HDL语言，编程实现上述功能。-Stopwatch
multi
- VHDL Multiplier RTL code-VHDL Multiplier RTL code
DDSsheji
- 再发一个修改的完善的基于FPGA的DDS信号源实现方案-Recurrence of an amendment to improve the FPGA-based realization of the DDS signal source program