资源列表
3-to-8Decoder
- 3 to 8 Decoder in vhdl
RippleCarryAdder
- Ripple Carry Adder in Vhdl
fifi
- FIFO code written in VHDL
usb_xilinx_vhdl
- FPGA核心部分源码，了解FPGA运行原理-FPGA core of the source code to understand the operating principle FPGA
music
- 用VHDL 语言设计实现一个10 秒倒计时电路，要求使用8×8 点阵显示计时结果。能在计时到0后开始播放乐曲，同时乐曲可以自由转换。-VHDL Language Design and Implementation with a 10 seconds countdown circuits require the use of 8 × 8 dot matrix display time results. To 0 in time to start playing after the music, a
usbip
- USB接口控制器参考设计，xilinx提供VHDL代码 -USB interface controller reference design, xilinx provide VHDL code
FPGAcoreofthesource
- FPGA核心部分源码,了解FPGA运行原理-FPGA core of the source code to understand the operating principle FPGA
vhdsincos
- 三角函数硬件实现代码，VHDL代码，供参考学习-VHDL build Sin Cos
jianpankongzhi
- 键盘控制米字管显示十进制，这是用MAXPLUS2做的仿真的全部文件。里面包含的仿真的全部结果-Keyboard to control the word-meter display decimal
s1_core.tar
- SPARC model verilog HDL
ad9826
- ADC8926 控制部分代码，内涵时序波形，和作业相关要求。-ADC8926 control part of the code
FREDIV
- 无限分频器,VHDL编写，可以实现奇数和偶数分频。-Unlimited divider, VHDL development, can be odd and even frequency.