资源列表
jishiqi
- 利用数字电路知识，进行二十四小时计时，并有闹钟与蜂鸣器功能-Knowledge of the use of digital circuits, the 24 hours time, and there is an alarm clock function and buzzer
PrimeTime_STA
- PrimeTime Intro to STA -PrimeTime Intro to STA
VHDL
- 关于VHDL编程的教程,比较系统的讲解,很有用的书-a book about VHDL
Microprocessor
- 精通verilog HDL语言编程的一个不错的cpu 代码-Verilog HDL language proficiency of a good cpu code
counter
- 一个用数码管自动计数的verilog程序，DE2开发板实现-An automatic digital control procedures verilog count, DE2 development board implementation
adder8
- Vrilog HDL 八位加法器源程序-8 adder Vrilog HDL source
mealy1
- mealy 状态机的独热编码源程序，接受么mealy状态机的编写规则。-mealy state machine of one-hot encoding source code, you mealy state machine to accept the preparation of the rules.
LS138
- 通过vhdl实现ls138硬件功能 通过vhdl实现ls138硬件功能 -the descr iption of ls138 in vhdl
hz
- 万能频率器，可以修改其中的参数，可是实现任意的分频！很方便！-Universal frequency, you can modify one of the parameters, but any implementation of the sub-band! Very convenient!
VHDLexample
- here is a VHDL example
clk_div
- VHDL描述的时钟分频电路，用途广-VHDL descr iption of the clock divider circuit, uses widely ...
fenpin
- 此为EDA设计的分频器模块。可以实现三种不同的频率信号，可以通过使用者自由设置频率大小-This is the design of the divider module EDA. Can achieve three different frequency signals, users can freely set the frequency of the size of