资源列表
dmx512
- DMX512接收程序C源代码，DMX512接收程序-C source code of the receiving program DMX512, DMX512 receiving program
shuzishizhong
- 此代码是FPGA的数字时钟代码，使用的是verilog语言。-This code is the FPGA' s digital clock code, the use of the verilog language.
Writing_Testbenches_using_System_Verilog
- Testbench creation and development methodology with System Verilog. By Janick Bergeron.
dds-design
- fpga实现dds，实现任意波形输出信，设计代码verilog-dds fpga realization
SDRAM
- sdram的学习使用控制源代码 有需要的同学可以下载-sdram learning to use the control source code can be downloaded to needy students
iic
- 单片机和cpld通信中的用vhdl编写的cpld源程序代码-Cpld single-chip computer and communications cpld prepared using vhdl source code
verilog_18bit_Div
- verilog编写的18位输入高精度的除法器，带说明文件和测试代码。-18 input precision divider verilog prepared with documentation and test code.
i2c
- 标准I2c读写时序，verilog Hdl-Standard I2c read and write timing, verilog Hdl
FPGA_experience
- FPGA设计经验总结，对你的FPGA设计能力将有很大的提高-The summary of FPGA s design, it will be a great improve to your ability of designing FPGA
PCK_CRC32_D8
- VHDL实现的8位数据，CRC32的实现代码，简单实用-VHDL achieve 8-bit data, CRC32 implementation of the code, simple and practical
24_bit_register
- 自己使用VHDL语言编写的24位寄存器.主要用于DDS中-24bit_register
cos
- FPGA实现正弦，余弦的计算，verilog语言-FPGA realization of sine, cosine calculation, verilog language