资源列表
Implement-a-CPU
- 在FPGA赛灵思基础3上使用Verilog HDL实现支持MIPS操作子集的CPU-Implement a CPU which supports a subset of MIPS operations using Verilog HDL on FPGA Xilinx Basys 3
forwarding
- 浙江大学体系结构实验课代码，5级流水线实现旁路和停顿-5-stage pipeline to achieve realization of the bypass pipeline bypass pause 5 pause
uart_VHDL
- VHDL写的串口程序，调试通过，有兴趣的朋友可以看一看-VHDL write serial programs, debugging through, interested friends can look at
lcd1602_testshiyan4
- 液晶lcd1602的verilogHDL显示程序-verilog HDL lcd1602 liquid crystal display program
VerilogHDL
- 复杂数字电路与系统的VHDL设计方法，有原理，说明及实例-Complex digital circuits with VHDL design system, a principle, descr iptions and examples of
verilog--uart--fpga
- 基于verilog的串口通信实验指导和源程序-Verilog based serial communication experiment guide and source code
ddrct_gen_xp_1_002_1
- ddrct_gen_xp_1_002_1，有关ddr控制的设计程序
VHDLexample
- VHDL设计实例 希望对学习VHDL开发的同学有所帮助！-VHDL Design Example hope to learn VHDL help students develop!
CycloneIII_EP3C40F780C8_6_Timers
- SOPC,CycloneIII系列芯片EP3C40F780C8，NIOS II IDE,定时器实验代码-SOPC,CycloneIII，EP3C40F780C8，timers code
VGA-(1)
- 基于FPGA的VGA接口代码，引脚已按装好，板子DE2-115-Based on FPGA of VGA interface code, the pin has been installed, board de2
cordic
- cordic processor descr iption
cf_fft_latest.tar
- FFT eficient, This code implements FFT for any application