资源列表
cf_fft_latest.tar
- This a code for FFT in VHDL, Verilog & C Source: OpenCores.org-This is a code for FFT in VHDL, Verilog & C Source: OpenCores.org
cf_fft_latest.tar
- The FFT architecture is pipelined on a rank basis each rank has its own butterfly and ranks are isolated from each other using memory interleavers. This FFT can perform calculations on continuous streaming data (one data set right after anot
cf_fft_latest.tar
- 整个设计使用了流水线设计，运用了同步的使能和复位信号。这是一个4k点的fft。实部和虚部均为18bit，总共为36bit精度。-All designs are pipelined with a synchronous enable and reset. 18 bit precision, real and imaginary. Total is 36 bits.
work_1
- spartan 3e-500 lcd 显示的数字钟，能显示年月日时分秒，以及星期还有闹铃时间，时间闹铃等可以自动调节，还有电台报时功能。星期模块有些许问题，调年月日的时候星期不会自动跳变，需要自己重新调，正常计时会自动跳变。-Spartan 3 e- 500 LCD display digital clock, can show minutes when (date) (month) (year), and week as well as the alarm time, time can aut
A-Verilog-HDL-Primer
- 老外写的经典verilog书籍二 the A Verilog HDL Primer -Classic books written by foreigners verilog two the A Verilog HDL Primer
IDEA
- IDEA算法硬件实现，可以在ise系统上实现-IDEA algorithm implementation
03_key_detect_1
- 键盘抖动的Verilog实现，设计的方法主要是由“电平检查模块”和“10ms延迟模块”组合合成。-Keyboard shaking Verilog implementation, the method of design is mainly by level examination module and 10 ms delay module combinatorial synthesis.
ISP_FPGA_PAPER_02
- 单片CISAF模块设计及其在监控系统中的应用研究.kdh-Single CISAF module design and its application in the monitoring system. Kdh
XuLie
- 序列检测机，可检测8位数字序列，米勒型状态机-Sequence detector can detect 8-digit sequence, Miller-type state machine
SDRAM-control-SOPC
- sdram 控制器的sopc搭建 sdram 控制器的sopc搭建 -sdram controller the sopc build sdram controller sopc structures the
ISEexamples
- VHDL and Verilog design examples.-VHDL and Verilog design examples.
test_sdram
- 对SDRAM进行读写，工程内部分为PLL以及复位处理模块、写SDRAM逻辑模块、读SDRAM逻辑模块、SDRAM读写封装模块、读写缓存FIFO模块、串口发生模块等。工程基于altera的Quartus II 10.1进行设计，使用更高版本的软件均可。-SDRAM read and write for the project is divided into the internal PLL and reset processing module, SDRAM write logic block,