资源列表
UART_source
- 用VHDL编写的UART源程序，请需要的朋友下载-VHDL source files prepared by the UART, please download a friend in need
VHDL
- 运用vhdl程序设计语言进行ppm设计，ppm 设计在vhdl语言中非常常用，运用已经越来越广泛。-use vhdl program design language ppm design, vhdl ppm design in a very common language, has become increasingly widespread use.
bijiaoqi
- 应用vhdl语言进行加法器的设计，比较器的设计，随着vhdl语言的应用越来越广泛，其重要性也更加明确。希望对大家有所帮助。-application vhdl language adder design, compared with the design, With vhdl language widely used, the importance of which was more explicit. We want to help.
ram
- 本原代码中利用VHDL语言编写了RAM、FIFO、ROM等常用的存储和缓冲部件，完全的代码在ALTERA的FPGA上已经通过仿真测试，保证可用.-primitive code using VHDL prepared RAM, FIFO, ROM, and other commonly used storage and buffer components, complete code in the Altera FPGA simulation test has been passed to ens
chap5
- 《Verilog HDL 程序设计教程》2-"Verilog HDL Design Guide," 2
chap6
- 《Verilog HDL 程序设计教程》3-"Verilog HDL Design Guide" 3
chap7
- 《Verilog HDL 程序设计教程》4-"Verilog HDL Design Guide" 4
chap8
- 《Verilog HDL 程序设计教程》5-"Verilog HDL Design Guide" 5
chap9
- 《Verilog HDL 程序设计教程》6-"Verilog HDL Design Guide" 6
chap10
- 《Verilog HDL 程序设计教程》7-"Verilog HDL Design Guide," 7
chap11
- 《Verilog HDL 程序设计教程》8-"Verilog HDL Design Guide" 8
chap12
- 《Verilog HDL 程序设计教程》9-"Verilog HDL Design Guide" 9