资源列表
UART_16750_vhdl
- UART串口FPGA源文件，VHDL设计文件，兼容16750-UART FPGA VHDL 16750
jpb_ise12migration
- 旋转编码 功能性键盘编码 spi时序发送数据-cycle key code
music
- Music demo verilog file
VERILOG-Simulation
- This VERILOG simulation example shows a 16 bit group ripple adder circuit for FPGA. The netlabel is used to split 16 bit bus to four 4 bit bus and connect them to four 4 bit adder. The result is joined to a 16 bit bus using netlabel. The Simulation c
16Bit-Group-Ripple-Adder
- Verilog Testbench for 16Bit Group Ripple Adder
BCD-Counter
- Verilog Module for parity
Error-Correcting-For-7bit-Hamming-Code
- Verilog Module for a 3 to 8 bit decoder
Frequency-Meter
- Verilog Module for 7-Segment-Display Decoder for Common-Anode LED
Parallel-To-Serial-Converter
- Verilog Module for 8-Bit Loadable Serial/Parallel-In Parallel-Out Shift Registers with Clock Enable and Asynchronous Clear
pgm
- package for image reading and writing in vhdl
Add2bits
- add 2 bits and display result on 7 segment (vhdl)
soc_ip-2016-10-12
- 基于ISE14.7，软核SOC的自定义IP核源码，8个寄存器，全部引出，可以作为FL-FS通讯接口，附带几个其他驱动IP核-Based on the ISE14.7, soft-core SOC custom IP core source code, 8 registers, all derived, can be used as FL-FS communication interface, with several other drivers IP core