资源列表
HCIUART
- 蓝牙HCI—UART与并口的FPGA控制接口设计-Bluetooth HCI-UART and parallel port control interface of the FPGA design
rotary
- Spartan 3E上的Rotary encoder控制程序，及验证它的小灯程序-Rotary encoder on the Spartan 3E control procedures, and verification procedures for its small light
liushun
- 流水灯和跑马灯的程序 已经编译 可以用 是quartus的开发环境-Marquee lights and running water has been the procedure can be used to compile the development environment is quartus
FPGA_DSP_using_matlab
- 这是一个使用matlab语言来实现FPGA的DSP算法的例子。主要是针对xilinx的FPGA芯片。这是一种比较新的编程方法，让matlab工程师也能快速的进行硬件编程。-This is a language to use matlab to implement FPGA-DSP algorithm for example. Mainly aimed at xilinx FPGA-chip. This is a relatively new programming method, so that
xilinx_edk_9.2_crack
- xilinx edk 9.2 破解器/注册机-xilinx edk 9.2 crack
VHDL_logic_v3
- Altera USB-BLASTER 源码-Altera USB-BLASTER source
XilinxISE9.2andChinpScopePro9.2Sn
- Xilinx ISE 9.2 and ChinpScope Pro 9.2 Sn
atan
- 自己写的cordic 的 64位计算反正切的程序，-cordic count atan program
FIFO_Design
- 一种基于格雷码的异步FIFO设计与实现,8*8位的fifo VHDL 源码-Gray-code based on the Asynchronous FIFO Design and Implementation
lvpecl_connect_lvds
- 在FPGA间实现LVDS和LVPECL互联时的用法，比如如何做匹配网络-Achieved in the FPGA LVDS and LVPECL interconnection between the time of usage, such as how to do the matching network
fir
- 用VHDL语言设计有限脉冲响应的FIR滤波器。用户可以在Xilinx ISE环境下运行。-With VHDL language design finite impulse response of FIR filter. Users can run Xilinx ISE environment.
lift-verilogHDL
- 利用verilog语言实现一个简单的电梯控制，可借助最小系统开发板进行试验-control lift by using verilong HDL