资源列表
24Bit_Spi
- 24位数据转化为SPI指令，注释详细，位宽可自行更改，适用于多位数据转化为串行数据，实测可用-For SPI instructions, detailed notes, bit width can be self change, applicable to a number of data conversion for the serial data can be measured 24 bit data transformation
eluosi_game
- 使用Quartus II 9.1完成俄罗斯方块游戏，只要使用有VGA和键盘接口的FPGA开发板就行实现。操作简单，使用的是VHDL和Verilog语言-Use the Quartus II 9.1 to complete the tetris game, as long as you use a VGA and keyboard interface implementation of FPGA development board. The operation is simple, the use
fpga-fir
- 使用Quartus II 9.1完成低通FIR滤波器的实现，在任意开发板上都能实现。操作简单，使用的是VHDL和Verilog语言-Use the Quartus II 9.1 the realization of the complete low pass FIR filter, can be implemented in any development board. The operation is simple, the use of VHDL and the Verilog langua
post_norm_fmul2
- Post_norm_fmul2 vhdl code
mulfp
- Mulfp for vhdl coddin-Mulfp for vhdl coddingg
FLOAT
- Floating point vhdl coding
fpu_arch
- Floating point architecture
khanom-heydari
- Floaaattiing poiiint for vhd-Floaaattiing poiiint for vhdlll
polyphaseFIR_1v0
- polyphase fir dilter
reset_syn
- 复位信号的处理，实现“异步清零，同步释放”的功能。-Reset signal processing, " asynchronous clear, synchronous release" function.
clk_div
- 时钟分频功能模块，采用计数器后两位异或再移位的方式实现，节约资源。-Clock divider function module, after using two different counter or re-shift ways to save resources.
rs422_r
- 此功能模块实现了422标准协议的单字节接收功能，采用了起始位＋8位数据位+奇校验+1停止位的方式，实现了串行输入并行输出的功能。-This function module implements the standard protocols 422 single-byte receive function, using the start bit+ 8 data bits odd parity+1+ stop bits, enabling a serial input parallel outpu