资源列表
YCbCr2RGB
- YCbCr turn RGB module, to apply to the project.
test-led
- 流水灯程序，利用了VHDL，虽然程序比较简短，但是，用的还是比较经典的-Light water program, the use of VHDL, although the procedure is relatively short, but with quite classic
7210040034_Yasifa-Rakhma_ProjectAkhir
- REPORT OF Embedded System VHDL 3-to-8 Decoder using a For-Loop
SD_Card
- sdhc卡spi扇区读verilog例程。包含sdhc卡初始化模块及一个扇区读模块，扇区读完数据放在一个fifo中缓存，为之后的工作做准备，可以集成到自己的项目中。已经在闪迪8Gsdhc卡上亲测成功-sdhc card sector read spi verilog routine. Initialization module and a read module contains sdhc card sector, the sector read data in a cache fifo in
verilog
- verilog的基础入门资料，很适合初学者学习参考-verilog basis for introductory information, it is suitable for beginners to learn reference
stopwatch_if
- 用IF语句实现秒表功能的代码，显示范围在000至9-Stopwatch function code with the IF statement, displayed in the range of 000 to 99.9.
FIFO_BUFFER
- 先入先出的缓冲器，可以实现8位的读、写数据操作。-buffer of first-in first-out circuit can ，Realization 8-bit. The number of read and wirte operation is stopped.
free_running_counter
- 这是一个计数器，可以实现自加1操作的自动计数器。-this is a counter ,By Mika realization operational counter add 1.
dual_priority_encoder2
- 这是一个组合电路，实现的是8位的优先编码器。-this is a combination circuit,Implement the eight priority encoder，
DATA_SEND1
- vhdl code for w300 and I doenload @ chines site
eetop.cn_dds
- 基于verilog的DDS设计,内附代码,仿真环境等说明-the DDS design based on verilog
0714
- 这是一个简单的基于VHDL的初学者编写的功能丰富的电子钟.-This is a simple VHDL based program for beginners to write a rich electronic clock.