资源列表
lock2
- 使用VHDL语言，实现了一个四位二进制串行密码锁-VHDL language to achieve a serial lock
JiShuQi
- 实现了一个秒表计数器，输入为2MHZ时钟，使用VHDL语言实现-It implements a stopwatch counter input 2MHZ clock, using VHDL language
clock
- basys2 四位数码管计时器 0 到999.9秒-basys2 four digital timer 0 to 999.9 seconds
micro_complet
- this is descr iption of microprocessor 8 bits in vhdl. enjoy
fifo_srl_uni
- asynchronous fifo in vhdl
AntiLog2
- fasto algorithm for inverse logarithm in verilog
src
- heap sorter algorithm in VHDL
RTL
- PWM controller in VHDL
src
- IQ correction module in VHDL
PULSE_CDC
- Clock Domain Crossing (SLOW-to-FAST OR FAST-to-SLOW). This module transfers pulse IN clock domain to OUT clock -Clock Domain Crossing (SLOW-to-FAST OR FAST-to-SLOW). This module transfers pulse IN clock domain to OUT clock
hostreg_make
- Verilog register creator based on text file input.
CIC_interpolator_wer1
- CIC interpolation filter which DOESNT WORK-CIC interpolation filter which DOESNT WORK!!