资源列表
VGA_DATA
- Create VGA module using VHDL on Altera DE2. It is better if you understand the full theory of VGA.
DE2_115_Audio
- This a shared & storage file, which was written by Altera. It is quite possible that Applications will use this sample.-This is a shared & storage file, which was written by Altera. It is quite possible that Applications will use this sample.
DE2_115_TV
- This an application of FPGA which wrote by Altera. It can be used for interfacing VGA, SDRAM on DE2-115-This is an application of FPGA which wrote by Altera. It can be used for interfacing VGA, SDRAM on DE2-115
lcd1602
- 本程序是1602型LCD的字符显示程序，可以直接下载使用。-This program is a 1602-type LCD character display program, you can directly download.
RS-encoder
- RSC encoder in VHDL. Hope it helpful.
V2.tar
- SDIO slave, written in verilog, does not support SPI mode.
APB_slave
- APB slave template for AMBA bus written in Verilog
or1200.tar
- OpenRISC 1200 cpu with integrated patches to support ORPSOC and FuseSOC builders
verilog-arbiter.tar
- Verilog arbitrator for Wishbone R3 compliant bus
wb_sdram_ctrl.tar
- Generic Wishbone R3 compliant SDRAM controller written in Verilog
bt656_timing_analysis
- BT656信号分析参考规格书，对分析bt656信号非常有帮助-The video standard ITU-R.656 timing analysis
Basys2Lcd
- This the file of controling a LCD display of Basys2 board used to pass the exams of VHDL-This is the file of controling a LCD display of Basys2 board used to pass the exams of VHDL