资源列表
code
- these are some of the codes for vhdl
key44
- 4*4按键扫描VHDL程序 在开发板上调试成功,放心使用 -4* 4 keypad scanning process in the development of on-board VHDL debugging success, rest assured that the use of
mc8051_design
- MC8051 core , VHDL , Oregano Systems
CRC_Generator
- This a binary encoded on the check, by check, to verify whether the correct transmission-This is a binary encoded on the check, by check, to verify whether the correct transmission
quartus
- des algorithm send rx from serial port
7
- vhdl七段数码管显示程序，上机实验过，完全正确-Seven-Segment LED display vhdl procedure on the experimental machine, and absolutely correct
1616
- 用vhdl语言描述的16*16点阵显示英文字母-Vhdl language used to describe the 16* 16 dot matrix display alphabetical
fpgafifo
- 基于fpga 实现 fifo 基于FPGA的非对称同步FIFO设计-Fpga-based FPGA-based realization of fifo asymmetrical design of synchronous FIFO
1
- 一本很好的VHDL教程-A very good VHDL Tutorial。。。。。。。。
modelsim
- modelsim的详细教程，请大家笑纳-very good！
vhdl
- ：以上海地区的出租车计费器为例，利用Verilog HDL语言设计了出租车计费器，使其具有时间 显示、计费以及模拟出租车启动、停止、复位等功能，并设置了动态扫描电路显示车费和对应时间，显示 了硬件描述语言Verilog—HDL设计数字逻辑电路的优越性。源程序经MAX+PLUS Ⅱ软件调试、优 化，下载到EPF1OK10TC144—3芯片中，可应用于实际的出租车收费系统。-: A Shanghai taxi meter area for example, the use of Veri