资源列表
count64
- 将5MHz时钟信号分频后得到1.6/3.2秒可选的同步信号，还可接外接同步信号对其进行强制同步-To 5MHz frequency clock signal 1.6/3.2 seconds after the optional sync signal, external sync signal can then be forced synchronization
modifiedBoothMultiplier
- verilog code for modified booth multiplication using maxplus2
shiyan3
- 为c++类模块的调用，必须在c++环境中使用-For c++ class module of the call, must be c++ environment
DM134b_Test
- 点晶DM134B恒流驱动芯片测试程序，包括20mA和40mA测试，FPGA采用LATTICE的M4A5-Point crystal DM134B constant current driver IC testing procedures, including the 20mA and 40mA test, FPGA using M4A5 of LATTICE
Ram_interface
- VHDL Ram interface which devaloped for 256K ram -VHDL Ram interface which devaloped for 256K ram
CRC
- 关于通信系统中循环差错检测的vhdl仿真程序，内容十分完整-Communication systems on the circle of error detection of vhdl simulation program, very complete
elevator
- 这是一个小课程设计，关于电梯控制的vhdl仿真程序，内容十分完整-This is a small curriculum design, on the elevator control of vhdl simulation program, very complete
wave_generator
- 这是一个关于信号发生器的vhdl仿真程序，内容十分完整-This is a signal generator on the vhdl simulation program, very complete
suanfa
- 算法硬件实现，学习的好资料，来自北航夏宇闻老师，VERILOG。-Algorithm for hardware implementation, learning good information, hear from teachers BUAA Xia, VERILOG.
THS1206
- FPGA来实现数据采集，AD采用TI公司的THS1206，高速并行AD，内含16字FIFO，降低硬件复杂度。-FPGA to realize data acquisition, AD using TI company s THS1206, high-speed parallel AD, containing the 16-character FIFO, to reduce hardware complexity.
dac
- 0～5伏可调数字电压源，以5伏为基准电压，数码管显示当前电压值，使用VHDL语言实现，程序都加了注释，方便阅读。 -0 ~ 5 V digital voltage source adjustable to 5 V for the voltage reference, digital tube displays the current voltage value, the use of VHDL language, the program notes are added to facilita
eff1
- 利用Verilog实现的跑马灯，从护栏管的一端循环到另一端。其他类似此类的循环语句基本一样。-Marquee achieved using Verilog, from one end of tube to the other end of the cycle. Other similar expressions of such basic, like the cycle.