资源列表
16QAM
- 使用verilog编写的16QAM调制解调代码，可用于quartus和ISE，因为不包含FIR，只能用于仿真，不能用于实际通信-Verilog prepared using 16QAM modulation and demodulation code can be used quartus and ISE, because they do not contain FIR, only for simulation and not for actual communication
jiao-tong-deng
- VHDL语言设计交通信号指挥灯自动指挥的设计-VHDL language design traffic signal lights automatically directing the design of the command
CISC-Processor-MOdule-Verilog
- Cisc Processor For Se-Cisc Processor For Sell
exercise
- 功能简单的测试文件,主要是对于初学者自己玩玩就好了-simple and easy
lab4_5
- 用VHDL实现串行除法器，16位被除数，8位除数-Using VHDL serial divider, 16 dividend, divisor 8
eth_Management_interface
- FPGA verilog simple MAC 源码-FPGA verilog simple MAC source code
fsmled
- verilog语言, 状态机实现数码管显示 -This uses verilog language to make state machine realization of digital control
FFT.vhdl
- FFT algorithm to implement FFT chip.
smii-to-mii
- SMII 到 MII 转换的VHDL代码
main
- 嵌入式OV7670摄像头的应用程序源代码，可以作为二次开发的参考程序。-Embedded OV7670 camera application source code, can be used as a secondary reference for the development process.
dds_gen
- 基于FPGA的频率相位可调DDS信号发生器-FPGA-based phase adjustable frequency DDS signal generator
chu_zhu_che_jijia
- 主要完成了出租车计价器所有功能的模拟程序，经过硬件电路调试已获得成功。-Completed the main taxi valuation implement all functions of the simulation program, through the hardware circuit debugging has been successful.