资源列表
chap3
- Verilog源代码一共135例chap3-chap12，初学必备-Verilog source code for a total of 135 cases of chap3-chap12, beginner necessary
xchengxu
- 数字密码引爆器顶层设计，VHDL结构描述程序
LL
- verilog语言的异步接口转换设计程序代码.-verilog language the asynchronous interface converter design code.
LL
- verilog语言描述的异步FIFO设计。-verilog language to describe the asynchronous FIFO design.
fsmd_examples
- fsm有限状态机加datapath的一个例子-fsm finite state machine plus datapath example
spi_flash
- FPGA中的EDK中实现对spi_flash的读写操作，程序适用于flash型号为N25Q128，当然将头文件中的flash参数修改后，即可用于其它flash-EDK in the FPGA to read and write operations of spi_flash procedure applies to the flash model N25Q128 , of course, modify the header files in the flash parameters can be
VGA
- 时序逻辑 VHDL 实现VGA显示接口 串口连接-vhdl vga
CU
- mips指令控制器。fpga上板验证实现。为cpu课设重要模块-mips instruction controller.
LedCube
- LedCube for students.
DCT
- Discrete Cosign Transform(DCT) Verilog Source Code
VERILOGTIME
- 利用10M 的时钟，设计一个单周期的周期波形-use 10M clock, the design of a single-cycle waveform cycle
AES
- AES的加密解密verilog全部源代码-AES encryption and decryption verilog full source code