资源列表
write_reg
- 用VHDL语言编写的写存储器程序，可下载在FPGA中使用-VHDL language used to write memory program can be downloaded in the FPGA using
LIP1771CORE_i2m_tb
- I2M CORE include i2c, spi slave Module and test bench
若干74HCxxx的Verilog源码。
- 包括：74HC85、74HC138、74HC161、74HC151、74HC373 74HC4017、74HC238、74HC194等器件的Verilog编码实现。为.V文件，也可直接用记事本等打开。
Verilog74HCxxx
- 文档为用verilog编写的若干74hc系列器件的HDL实现。包括：74HC85、74HC74、74HC138、74HC151、74HC161、74HC194、74HC373、74HC283、74HC4017等-Documents prepared for the use of verilog series devices HDL certain 74hc implementation. Including: 74HC85, 74HC74, 74HC138, 74HC151, 74HC161,
tcdg.vhdl
- des vhld 源码 程序完成了DES的编码和解码功能-des vhld source procedures completed DES encoding and decoding
lab4
- 创建一个digital system，让它可以计算:F0 (X+Y)/2-1,F1 (X+Y)/4-1,建立datapath和control unit，最后烧录进板子里观察屏幕示数和led亮灭。-(X+Y)/2-1, F1 (X+Y)/4-1, u5EFA u7ACBdatapath u548Ccontrol () () () () () () () () () () () () () () () () () () () () () () () () () () () () () ()
ytupn
- Very suitable for the study using computer vision, Analysis of the signal time domain, frequency domain, cepstrum, cyclic spectrum, etc. The performance of the program has reached a high level.
traffic-light
- 基于VHDL语言开发实现交通灯的功能,实现倒计时，直行，向左转向右走的功能控制-traffic light design
progconterful
- four bit counter verlog source code for veriwell including test bench-four bit counter verlog source code for veriwell including test bench
Crack_QII60_b178
- 为一个自学vhdl的有效文集，希望能帮到大家
code
- nice book and also nice programmme if any body try to understand easily understandable badhu mafat joie che
continue_bus_sync
- continue asynchronous bus exchange write by verilog cdoe