资源列表
The-key-control-divider
- 这是一个利用VHDL代码编写通过按键控制的分频器，通过给按键s3、s2、s1、s0赋不同的值，可以使分频器输出不同频率，此代码原用于自制示波器的分频。-This is a use of the VHDL code written by key control divider divider output through to key s3, s2, s1, s0 endowed different values, different frequencies, this code is the o
SDR
- FPGA based implementation of a SDR - codes in Verilog HDL for the processor and control.-FPGA based implementation of a SDR- codes in Verilog HDL for the processor and control.
szdyb
- 关于数字电压表的vhdl实现，有仿真程序，可以下载到板子中。-Vhdl digital voltage meter on the implementation of a simulation program can be downloaded to the board.
concurrent
- truong trinh tinh toan truc tiep cac toan tu
adder
- VHDL Adder implementation done in FPGA environment. VHDL Adder implementation done in FPGA environment.-VHDL Adder implementation done in FPGA environment.VHDL Adder implementation done in FPGA environment.VHDL Adder implementation done in FPGA envir
qiang-da-qi
- VerilogHDL 语言实现的四路抢答器-VerilogHDL language Quad Responder
S5
- VERILOG SOURCE CODE FOR N MODULO COUNTER
chap12
- 本程序是关于学习VERILOG语言的案例，方便读者快速掌握VERILOG语言的基本语法，操作等-This program is about learning the language of the case VERILOG to allow readers to quickly master the basic syntax of the language VERILOG, operation, etc.
sd_spi_model.tar
- SD card, SPI mode, Verilog simulation model
manchesteruart_latest.tar
- Manchester编码转uart的vhdl 代码-Manchester to uart
FIFO
- 异步FIFO控制器的Verilog设计与实现
DW_ahb_dmac_sbiu
- designware提供的dmac slave接口硬件描述语言-designware provide the source code verification VIP FIFO