资源列表
jiajian
- 利用Verilog语言编写的按键实现数码管显示数字的加减,通过三个按键分别实现加1和减1操作 以及复位操作,BASYS2开发板验证。-Verilog language use buttons to achieve digital display digital subtraction achieve plus one and minus one operation and reset operation, BASYS2 development board were verified by thr
ram
- 基于altera ep2c8双口RAM -Altera ep2c8-based dual-port RAM
ldpc_decoder_802_3an_latest.tar
- 802.3an ldpc decoder verilog 源码
ldpc_decoder_802_3an_latest.tar
- 适用于10GBase-T的以太网(802.3an协议)LDPC解码器, 用VHDL语言编写,可以应用在LATTICEXP2系列芯片上,基于Gallager算法。-LDPC decoder for 10GBase-T Ethernet (802.3an), based on Gallager s A algorithm
ldpc_decoder_802_3an_latest.tar
- ldpc decoder 802-3an,最新版本,verilog版本.完成基于LDPC解码 -ldpc decoder 802-3an, the latest version, verilog version. LDPC decoder based on the completion
Design_and_Analysis_of_Electronic_Code_Lock
- 电子密码锁的设计与分析__系统设计要求/系统设计方案/主要VHDL源程序/系统仿真/硬件验证/设计技巧分析/系统扩展思路-Design and Analysis of Electronic Code Lock
S7_PS2_RS232
- 本实验实现PS/2接口与RS-232接口的数据传输, PS/2键盘上按下按键,可以通过RS-232自动传送到主机的串口调试终端上(sscom32.exe); 并在数据接收区显示接收到的字符。 串口调试终端的设置:波特率115200,一个停止位,无校验位。
TrabPrat_70889
- exemplo codigo vhdl no ise
8bit_up
- 8 bit microprocessor made3 by iitd
24T
- 24小时周期时钟设计,通过quartus模块实现24小时周期时钟,包含模拟的时钟脉冲。-24 hour cycle clock design, through the quartus module to achieve a 24 hour cycle of the clock, including analog clock pulse.
sysemdesign
- 利用FPGA对信道传输后的信号进行采样并提取同步锁相的一种实现-The signal channel is sampled and a synchronous phase-locked extraction using FPGA
xapp1076
- Implementing Triple-Rate SDI with Spartan-6 FPGA GTP Transceivers
