资源列表
shuzi
- 讲述了全数字信号发生器部分频率值测算的表格-Full digital signal generator frequency value calculation form
verilog_example
- 九个verilog源码例子，包括寄存器，状态机等，含testbench-9 verilog source code examples, including registers, state machines, with testbench
8
- VHDL实验的程序，数字时钟，进行分秒计时，用数码管显示-VHDL experimental procedures, digital clock, for every minute timer with digital display
64bit_doublefloat_adder
- 64位双精度加法器 流水线四拍处理 将53位mantissa 扩展到80位-64bit adder
verilog_LCD1602
- verilog_LCD1602显示 8位输出-verilog_LCD1602 show 8bit output
chu_avalon_vga
- sopc builder ready vga controller
fifo_ctrl
- 好用的fifo控制verilog源代码，供大家学习参考，可以被综合。-Useful fifo control verilog source code for the study reference, can be integrated.
data
- 通过verilog hdl实现对数据的比较，分配器选择-Verilog hdl achieved through the comparison of the data, the distributor selection
diantiyunxing
- 能够实现电梯的基本运行功能，其中分为四个模块分开实现。-To achieve the basic operation of the elevator function, which is divided into four modules are implemented separately.
RAMINCREASE
- 这是利用ＣＰＬＤ做ＤＳＰ的存储器扩展的源文件。-CPLD This is done using the DSP memory expansion of the source document.
scaling
- A camera raw image file contains minimally processed data the image sensor of either a digital camera, image scanner, or motion picture film scanner. Raw files are named so because they are not yet processed and therefore are not ready to be printed
3
- 设计一个10进制同步计数器，带一个清零端，一个进位输出端。-Design a synchronous counter 10, with a clear end, a carry output.