资源列表
VHDL
- 上海交通大学VHDL课程的所有作业代码，欢迎有需要的XDXM光顾-homework of VHDL course at SJTU
verilog_m
- 用verilog生成的m序列，包含四个.v的文件-verilog m sequence
8位加法器
- 8位加法器的原代码,主要内容下载看了就知道-Adder eight of the original code, read the main content downloaded know
4Examples_VHDL
- vhdl的测试程序，进攻初学者使用，比较简单了，仅是测试程序。-VHDL test procedures, offensive beginners use, relatively simple, and only a test procedure.
S3_WAVE
- 1、模拟正弦函数发生器 2、可使用逻辑分析仪查看波形 -1, analog sine function generator 2，logic analyzer can be used to view the waveform
vendingmachinesource
- vendigmachine vhdl 5files component
verilog-hdljingyanji
- verilog,hdl经验集，讲得很好的-verilog, hdl experience set, put it very well
color1
- FPGA VGA彩条显示 vhdl编程语言-FPGA VGA color bar display vhdl programming language
Matlab
- 基于数字基带传输系统MATLAB仿真代码，以及相关文件。-Based on the digital baseband transmission system MATLAB simulation code, and related documents.
fft16
- this 16 point written in verilog-this is 16 point written in verilog
juzhenqufaqi
- 基于FPGA单精度浮点除法器的实现，有一些源代码，仅供参考。-FPGA-based single-precision floating-point divider realization, there are some source code, for reference purposes only.
Ms32pci
- PCI-ip硬件描述语言-开源的，可以做参考设计，如果需要的话，-This models are written in VHDL! Author is Ovidiu Lupas! MASTER model generates PCI compliant signals checks Target signal compliance with PCI checks data received from Target for correctness generates