资源列表
hdlc
- 基于FPGA的hdlc协议控制器的实现，用vhdl语言编写。-FPGA-based implementation of hdlc protocol controller, using vhdl language.
GPS_TX_RX_VERILOG
- GPS Tx RX verilog 19-GPS Tx RX verilog 1988
miaobiao
- 用Verilog HDL编写的秒表设计，可以实现百分之一秒，十分之一秒，秒，十秒等功能。-Verilog HDL prepared with a stopwatch designed to achieve the hundredth of a second, one-tenth of seconds, seconds, 10 seconds and other functions.
A-variety-of-dividers-program
- 各种分频器程序100倍分频器24998倍分频器2分频4分频 8分频16分频-A variety of dividers program
Source
- FPGA 上的嵌入式系统设计实例,spartan-3e-FPGA, embedded system design example, spartan-3e
11_vga
- This vga controller write in vhdl xilinx ise Connect your vga monitor and view many color in moniotr-This is vga controller write in vhdl xilinx ise Connect your vga monitor and view many color in moniotr
Cipher-lock.doc
- VHDL实现四位电子密码锁，并在12864液晶显示屏上显示-VHDL implementation of the four electronic locks, and 12864 on the LCD screen
adder
- A VHDL code for adding two numbers.It takes two 8bit words and give sum as output.
sdram_verilog
- 基于verilog语言的SDRAM控制器-SDRAM controller based on verilog language
encoder8_3
- 用VERILOG语言实现了常用8_3编码器.-Verilog language used to achieve a common decoder 3-8.-With the VERILOG language to implement common 8_3 encoder .- Verilog language used to achieve a common decoder 3-8.
std_logic_arith
- 一个用于转换设置，以及签署SMALL_INT，整数，STD_ULOGIC，STD_LOGIC和STD_LOGIC_VECTOR比较函数。-A set of arithemtic, conversion, and comparison functions for SIGNED, UNSIGNED, SMALL_INT, INTEGER,STD_ULOGIC, STD_LOGIC, and STD_LOGIC_VECTOR.
pos
- POS（10GE）verilog代码，加入到工程中就成为仿真平台POS发包、接收器。-POS（10GE）receiver and sender