资源列表
frequency_measuement
- 通过基4-fft算法测128点频率模块,其中包含所有需要的vhd文件，但是由于最多100M内容，因而需要用到的ipcore需自己添加。-128 points frequency measurement through based4-fft method,the folder involves all .vhl file,but it don t involves the ipcore due to the100M limit.
debouncer_vhdl
- debouncer in vhdl with clock devider parameter and number of inputs
de2_audio_if
- audio codec wm8731 wolfsom in verilog. custom project
Altera_QuartusII_13.0_Windows_Crack
- quartus 13.0 的破解文件 最新版本的破解文件-quartus 13.0 crack file latest version of the crack file
cputest
- 通过verilog语言设计的简单CPU，可完成加减乘除和算数逻辑移位功能。-By verilog language design simple CPU, to be completed by addition, subtraction, and arithmetic logic shift function.
DE2_VGA_pattern_gen
- VGA显示器控制，产生条纹。是学习VGA控制的良好参考资料。-VGA display control，To produce stripes
Nios_ii_8.0_back
- altera FPGA nios 实例，实现网络通信。-altera FPGA nios example, network communications.
Verilog-Quickstart
- verilog的很好的 学习书记，用于快速掌握开发，希望有用-verilog a good learning secretary for quickly grasp the development, I hope useful
EASYFPGA
- easyfpga的核心办及开发板的电路图，可以让需要的朋友借鉴下-easyfpga core Office and development board schematics, a friend in need can learn from the next
VGA
- 是配套与FUSION开发板上的VGA实验所用的完整工程，可以作为联系，让初学者快速掌握-Is supporting the development board VGA with FUSION used in the experiments of the complete works, can serve as a contact, so that beginners grasp
DM9000A
- DM9000网卡驱动控制器（SOPC控制核），适用于quartus8.0以上版本的Qsys，添加方法与SOPC_Builder一样，可直接调用-DM9000 network card driver controller (SOPC control of nuclear), applicable to quartus8.0 above version of Qsys, adding the same way as SOPC_Builder， can be called directly
Source
- 是FUSION开发板的PWM实验历程，可以用于初学者来借鉴pwm的生成-FUSION is experimental development board PWM course