资源列表
ADC_INTERFACE
- it is a verilog code written for MAX1886 ADC interin modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit. -it is a verilog code written for MAX1886 ADC interin modelsim simulator and it will synthesize in xinlix i
DMA-CORE
- simple verilog dma source
sssd
- MB CARD FPGA ENTERANCE FOR production lines to inc. process quality and monitoring process step by step phase for better under standing of manufac turing
example_mgt_top
- 用于光纤传输，详细叙述了整个过程的实现，以及时钟的实现。用来实现光纤传输过程编码-For optical fiber transmission, described in detail the whole process of implementation, and the clock to achieve. The process of coding for optical fiber transmission
boothmultiplier
- verilog code for 8-bit signed integers....its working
multiplier
- This file implemented a multiplier in VHDL
verilog1
- 此代码实现了n进制计数器，有清零。保持还有减一计数。-This code implements the n binary counter, there is clear. Keeping it there by a count
422
- files describe how to configure ADV7180- files describe how to configure ADV7180
VHDL
- 正弦波发生器代码VHDL 其中包括分频 正弦波数据-Sine wave generator VHDL code Divide the sine wave data including
7_lan
- 黑金开发板ENC28J60的Nios驱动-Black gold ENC28J60 development board driver
sdramc_controller
- sdram 控制器 用verilog语言实现 可综合-sdram controller can be integrated with the verilog language
led_run
- 基于FPGA的跑马灯VHDL设计程序，自己编译-Marquee VHDL FPGA-based design program, compile it yourself