资源列表
前面板装饰上色
- 本程序为版本labview2013，获取前面板引用句柄再获取装饰组，循环设置装饰颜色
foio
- verilog语言写的先进先出（FIFO）电路-verilog language written in FIFO (FIFO) circuit
2_instruction_decoding
- Risc processor:- instruction decode
3_execution
- risc processor:- instruction execution
rom_mod_sine
- Altera FPGA 从rom读数据，产生正弦波，modulsim仿真-Altera FPGA read data from ROM, produce sine wave, modulsim simulation
8220256202
- FPGA与CPLD的区别，仅供参考，好东西大家一起享用
26879085sttc4
- Package is for developing the g Encoding techniques and developed in the MATLAB
Laghi
- AD9850的控制源码，89c52控制，4*4键盘设计，8为数码管显示频率。-Control source of the AD9850, 89c52 control, 4* 4 keyboard design, digital display frequency.
8929736539335
- 貪食蛇程式寫作，主要說明貪食蛇吃蘋果及上下左右移動-Snake program writing
atapi_ctl_2_5
- fifo buffer vhdl code
dianhua-jifeiqi-verilog
- 电话计费器的verilog程序，希望对大家有用-Telephone billing verilog program
Sdram_Control_4Port
- ROM 控制，verilog 语言描述的，可直接编译，希望对大家有用-ROM control