资源列表
FIFO
- 三种同步方式实现的FIFO，verilog HDL，FPGA，更好理解FIFO-The three implemented synchronously FIFO, Verilog HDL, FPGA, a better understanding of the FIFO
nios-driverLCD
- 在FPGA中使用嵌入式软核NIOS2控制128*64的液晶屏程序-Embedded in an FPGA soft core NIOS2 control 128* 64 LCD procedures
RTL
- HMI产品上使用的将黑白屏提升分辨率变为彩色屏的verilog RTL code-verilog RTL code for convert Black/White HMI to high resolution color
FPGA
- 基于FPGA的直接数字频率合成器的设计实现和应用。-FPGA-based direct digital frequency synthesizer design and implementation and application.
Mul32
- Verilog语言编写的单精度浮点数乘法器-The Verilog language of single precision floating point multiplier
HW_songer_nverqing
- 用VHDL编写的播放器，播放西游记插曲《女儿情》，另附编码表WORD档-Using VHDL prepared player, player of Journey to the West episode
s25fl040a
- ST S25FL040 Sefial Flash Verilog Model
part3FSM
- Verilog FSM implementation for altera s lab(part 3 of lab 7).
processor
- verilog program for alu
UART
- VHDL实现UART通信,包括发送和接叫程序，使用方便
rom
- Read-only memory,Verilog code
UART_LCD
- 基于Actel的Fusion系列FPGA的UART串口，带FIFO-Based on Actel s Fusion Series of FPGA serial UART with FIFO