资源列表
freq_divider
- 一个时钟分频器，可以实现任意整数倍或者分数倍的分频功能。-A clock divider can be an arbitrary integer multiple or fraction of times the frequency function.
JKF.vhd
- pulse framing circuit
traffic
- DE2_traffic_light(in verilog source code)
COUNT60
- 60位进制计数器 可将程序下载后进行60进制表现 并应用于电子表运算-60 binary counter can download the program and after the performance of 60 binary operations used in electronic form
a-to-A
- 将字符串转换为ASICII，用于FPGA码表-from strings to ASICII
HDLC_controller.rar
- a verilog code for hdlc controller,a verilog code for hdlc controller
QPSK
- modelsim环境下QPSK解调电路的仿真-modelsim simulation environment under QPSK demodulation circuit
4fsk
- 数字通信系统4进制频移键控4ASK信号的调制的VHDL代码-Digital Communication Systems 4 MFSK 4ASK signal modulation VHDL code
ODff377
- 8Dflipflop source code on VHDL
Manchester-code-of-VHDL-program
- 利用FPGA实现硬件的VHLD语言的Manchester code。-Hardware implementation using FPGA VHLD language Manchester code.
FT_LUT6_L
- Verilog of XILINX LUT6 of Xilinx-Verilog of XILINX LUT6 of Xilinx
CSLA_32
- 32bit carry select adder