资源列表
src
- FIR滤波器的设计，完整包括RTL代码、testbench等，清晰易懂。-FIR filter design, complete coverage of RTL code, testbench, etc., clear and understandable.
misunderstanding_in_FPGA
- FPGA设计中的误解。包括成本节约，低功耗设计，系统效率，信号完整性，可靠性设计-FPGA design misunderstandings. Including cost-saving, low-power design, system efficiency, signal integrity, reliability design
fadder4
- 例化语句生成的四位全加器代码，写在word里了，也有MODELSIM测试代码-Four cases of full adder codes generated by the statement, written in the word again, and there MODELSIM test code
c74138
- 关于译码器138的硬件语言代码，是系统中经常使用的接口电路-About 138 of the decoder hardware language code, often used in the system interface circuit
examples
- verilog分频器～时钟为50hmz，波特率采用9600bps～
uartverilog
- Verilog Uart经典实例，适合初学者练手，建议收藏-Verilog Uart classic example, training for beginners hand, the proposed collection of
JF
- 设计一个小型加法电路，以DE2板上18个拨动开关作为两组输入，代表两组十进制数（1-9），用七段数码管显示两个加数以及输出的和。-Design a small adder circuit to DE2 board 18 toggle switches as two inputs, two representatives of the decimal number (1-9), with two seven-segment digital display and output and the ad
i2c_FPGA
- I2c for fpga,I2c for fpga
BI08D708048AD_V1_IPCore
- 基于SDRAM+CPLD+STM32的VGA显示的-SDRAM+ CPLD+ STM32 VGA-based displays
TheDifferencebetweenVHDlandVerologHDL
- VHDL与Verolog HDL具体的不同，包括整体结构，数据对象及类型，运算符号，语句子结构，附加结构等-The Difference between VHDl and Verolog HDL
div
- 这是一个基于CPLD的VHDL语言的分频例程-This is a CPLD-based crossover routine VHDL language
PWM
- 采用STC89C52单片机的定时器以实现两路PWM波输出，占空比、频率可调-Microcontroller timer used to achieve STC89C52 two PWM wave output, duty cycle, frequency adjustable