资源列表
SOU
- 这是用C写的正弦函数定点数据生成代码，内容是生成verilog中RAM或者ROM和Matlab处理时的所用的数据。-It is written with C fixed-point data generate code sine function, the content is generated verilog RAM or ROM, and Matlab in the processing of the data used.
half_add
- 半加器，可移植性很强，只需改变内部的数字，即可得到任意的加法器！-The counter, portability is very strong, only need to a change in the inside of the digital can get any counter!!!!!
STC12C5A60S2_UART2
- STC12C5A60S2的第二串口程序，本人亲自写的，绝对好用。-Second STC12C5A60S2 serial procedures , personally written , absolutely easy to use .
shift-register
- 一个8位的左右移位寄存器电路，输入为时钟信号CLK，方向控制信号D， 输出信号为每个寄存器的状态。 -An 8-bit left and right shift register circuit, the input of the clock signal CLK, the direction control signal D, the output signal of the status of each register.
counter
- 在FPGA 设计中，计数器可以用来对信号的变化情况进行计数，是经常使用的功能块。 这里设计的是一个2 位宽计数器，可以从00 计数到11，计数原则是在时钟信号的控制下，每个时钟周期计数一次。计数器属于时序逻辑电路。-In the FPGA, the counter can be used to count the changes in the signal, the function block is often used. Here design is a two-bit wide,
APB_slave
- APB slave template for AMBA bus written in Verilog
Array-multiplier
- Array muiltiplier verilog code.. 4 bit two inputs with 8 bit outputs
rom
- 生成rom的代码-The code generated rom.。。。。。。。。。。。
float_data_multiple_use_fixed_
- 采用fpga做小数运算的程序，使用了三级流水线技术，这是学习流水线和定点小数乘法很好的例子！,a program of float multiply, using 3-stage pipeline technology
mccd_capture
- 采用verilog语言，实现视频的采集。通过fpga控制，实现视频逐行采集。-The use of Verilog language, the implementation of video acquisition. Through the FPGA control, achieve progressive video collection.
subtractor3
- Verilog 3bit full subtractor module and tests build with predefined nor gates.
d_ff
- 带置位、清零使能的D触发器以及同步清零D触发器、异步清零D触发器-VHDL，DFF