在FPGA 设计中，计数器可以用来对信号的变化情况进行计数，是经常使用的功能块。

这里设计的是一个2 位宽计数器，可以从00 计数到11，计数原则是在时钟信号的控制下，每个时钟周期计数一次。计数器属于时序逻辑电路。-In the FPGA, the counter can be used to count the changes in the signal, the function block is often used.

Here design is a two-bit wide, and can count from 00 to 11, counting principle is under the control of the clock signal, each clock cycle count once. Counters are sequential logic circuits.