资源列表
Audio_DAC_FIFO
- 用于做多媒体缓存的源码 可以做整帧的缓存-SquiDeral- manipulating the cache usage of Your Audio.
vga_colors
- 在VGA显示器上显示8色竖彩条,使用verilog语言编写，quartusII编译成功-VGA monitor display in 8-color vertical color
RS_enc
- RS编码器设计，使用Verilog实现。-RS encoder design, Verilog implementation.
verilog-tetris-master
- An implementation of the Tetris game using Verilog and a Spartan fgpa board
TEMP-SENSOR
- Temperature Sensor with i2c peripheral
Audio_DAC_FIFO
- terasic的DM9000A模块源码，使用nios2做以太网应用的应该会用到-terasic the DM9000A module source, use nios2 do Ethernet applications should be used
gamefour
- 这是一个自动售货机程序实现，功能如下：1.按一下button1按钮，表示购买货物A，第一个LED灯亮；按两下button1按钮，表示购买货物B，第二个LED灯亮；按三下button1按钮，表示购买货物C，第三个LED灯亮，同时7段数码管显示所要购买货物的价格。 2.LED灯亮后，开始输入硬币。button2按一下，输入10元，按两下，输入二十元，以此类推；Button3按一下输入5元，按两下输入10元，以此类推；button4按一下输入1元，按两下输入2元，以此类推。7段数码管显示已投入的总
MX25L6445E
- spi flash 驱动程序 verilog-spi flash Driver verilog
ddc_sim
- Digital downconvertor simulator
VHDL
- 本代码为用VHDL语言设计实现加法器、减法器、乘法器，并提供了模块图，进行了波形仿真。-This code is for the use of VHDL Language Design and Implementation of adder, subtracter, multiplier, and provides a block diagram carried out a wave simulation.
Altera_exercise
- this vhdl code for altera using quartus II v14 developed for beginners of altera fpga. if any comment or difficulty feel free to ask friends -this is vhdl code for altera using quartus II v14 developed for beginners of altera fpga. if any comment or
linedet
- Program matlab describe line detection algorithm, we can use System Generator Tool with matlab to implement it in FPGA.